Verilog Lab Solutions

EE Summer Camp - 2006 Verilog Lab Objective : Simulation of basic building blocks of digital circuits in Verilog using ModelSim simulator Points to be kept in mind: • For getting points in any question, you will have to simulate the testbenches and show us the waveform files for each question on Sunday, 14th May, at 10:30 AM, in the VLSI Lab. • Consultation is allowed for questions 1 and 3 amongst students. • Consultation for questions 2, 4 and 5 is only allowed with us. • Please do not attempt to copy from each other or from internet. We would very much like to personally clear any doubts th