FSMs in VHDL Using Enumeration Data Types Consider a falling edge triggered FSM that performs the following state diagram functionality. We want to write a VHDL model using enumeration data types.
0X 0X 10 0X 11
This FSM is a Moore machine since its outputs (RST and SHIFT) are a function of the current state only. The four states in the state diagram have not been assigned and are represented by the variable names: Reset, BIST, Result, and NOP (all are valid VHDL names). Since the FSM is falling edge triggered, all state transitions occur on the falling edge of the clock (which we will assume
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